Invionics Blog SystemVerilog Insights: Do always_latch and always_ff provide any real value?

On the surface they seem like fantastic extensions to the language, enabling designers to more explicitly state their design and guide verification and synthesis in a meaningful way. Gone are the days of inferring intent! We can now state and create what we want. But digging into the LRM, we can see that always_latch and [...]The post SystemVerilog Insights: Do always_latch and always_ff provide any real value? appeared first on Invionics.